This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-157195, filed May 25, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a multi-layered wiring structure.
2. Description of the Related Art
In recent semiconductor technology, an interlayer insulating film must be made of a low dielectric constant film. In general, the low dielectric constant film has a low film density and is permeable to water. Even if a very small amount of water, which has a relative dielectric constant k as large as 80 (a maximum value), is contained in the low dielectric constant film, the dielectric constant of the low dielectric constant film inevitably increases. In order to ensure effective use of the low dielectric constant film, therefore, it is necessary to prevent water or moisture from entering the low dielectric constant film.
FIG. 12 is a plan view showing a semiconductor device according to the first example of the prior art, and FIG. 13 is a sectional view taken along line XIIIxe2x80x94XIII in FIG. 12.
As shown in FIGS. 12 and 13, a gate electrode 72 is formed on a semiconductor substrate 71. A BPSG (Boron Phosphorous Silicate Glass) film 73 is formed in such a manner as to cover the gate electrode 72. A contact plug 75 is formed inside the BPSG film 73. A first wiring layer 74 is formed on the BPSG film 73 in such a manner that the first wiring layer 74 is connected to the contact plug 75. A TEOS (Tetra Ethyl Ortho Silicate)-SiO2 film 76 is formed in such a manner as to cover the first wiring layer 74, and this TEOS-SiO2 is overlaid with a second wiring layer 77. The second wiring layer 77 is connected to the first wiring layer 74 by way of a via 78. A passivation film 84, which is made up of a PSG film 79 and an SiN film 80, is formed in such a manner as to cover the second wiring layer 77. A via ring 81, which is made by the first and second wiring layers 74 and 77, the contact plug 75 and the via 78, is formed along the periphery of a chip 70. The via ring 81 is intended to prevent cracks at the time of scribing.
In the structure of the first example of the prior art, the passivation film 84 is not a single-layer film. It is a laminated film made up of the PSG film 79 (or another type of SiO2 film) and the SiN film 80 formed on the PSG film 79. This laminated structure serves to suppress the total stress of the film. The structure of the first example of the prior art raises a problem if an opening is formed in the passivation film 84 to provide a pad window. If such an opening is formed, the PSG film 79 is exposed in the wall surface of the opening. Since the exposed portion of the PSG film 79 undesirably serves as an inlet of moisture, it is hard to prevent the water or moisture from entering the chip.
In the process of forming the contact plug 75 and the wiring layers 74 and 77 by use of an Al material, the via ring 81 serves to prevent water from entering the chip from the side portions of the chip. This advantage cannot be expected if the contact plug 75 is formed of W.
FIG. 14 is a plan view showing a semiconductor device according to the second example of the prior art. FIG. 15A is a sectional view taken along line XVAxe2x80x94XVA in FIG. 14, and FIG. 15B is a sectional view taken along line XVBxe2x80x94XVB in FIG. 14.
As can be seen from FIGS. 14 and 15A, in the case where the contact plug 82 is formed of W, the contact plug 82 easily separate from the semiconductor substrate 71. To prevent the contact plug 82 from separating from the substrate 71, a plug such as the via ring 81 of FIG. 13 is not easy to form. Although columnar contact plugs 82 can be formed instead as shown in FIG. 15B, gaps 83 are inevitably produced between the contact plugs 82. Since the multi-layered wiring structure cannot be completely covered, it is hard to prevent water from entering the chip 70 from the side portions of the chip.
As described above, the prior art is not effective in completely protecting the chip from moisture, which may enter the chip from the top, bottom or side portions thereof. In other words, the prior art does not enable effective utilization of the characteristics of a low dielectric constant film.
A semiconductor device according to one aspect of the invention comprises a first insulating film; a first wiring layer formed in the first insulating film; a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film; a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section; and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.
A semiconductor device according to another aspect of the invention comprises a first insulating film; a first wiring layer formed above the first insulating film; a second insulating film formed above the first wiring layer and the first insulating film, the second insulating film including a low dielectric constant film; a second wiring layer formed in the second insulating film and coupled to the first wiring layer through a first connection section; and a third insulating film formed above the second wiring layer and the second insulating film and serving as one of an interlayer insulating film and a passivation film, and at least one of the first and third insulating films being one of a film formed mainly of SiON, a film formed mainly of SiN, and a laminated film being the films formed mainly of SiON or SiN respectively.